FIG. 15 is a circuit diagram showing the basic configuration of a conventional shift register operable with power voltage V.sub.DD =5.0 V.
In FIG. 15, MST is the master latch, SLV is the slave latch, NTM1, NTM1n, NTMs, and NTS1 are transfer gates composed of n-channel MOS transistors with threshold value voltage V.sub.thN of about 1 V, IVM1, IVM2, IVM3, IVS1, IVS2, and IVS3 are inverters, DIN1, DINn, and SIN are data input terminals, and DOUT is the data output terminal.
Master latch MST is comprised of transfer gates NTM1, NTM1n, NTMs, and inverters IVM1, IVM2, IVM3.
Specific connections are that each input terminal of transfer gates NTM1, NTM1n, and NTMs is connected respectively to data input terminals DIN1, DINn, and SIN, and each output terminal of transfer gates NTM1, NTM1n, and NTMs is connected to the input terminal of inverter IVM1 and output terminal of inverter IVM2.
Also, the output terminal of inverter IVM1 is connected to the input terminals of inverters IVM2 and IVM3, and the output terminal of inverter IVM2 is connected to the input terminal of inverter IVM1.
Namely, inverters IVM1 and IVM2 are connected between the input terminal of inverter IVM3 and output terminal of each transfer gates NTM1, NTM1n, and NTMs in parallel with the input/output terminals in the opposite orientation.
Inverter IVM2 is constituted with a high-resistance type inverter for safe operation of the circuit and prevention of through current.
Slave latch SLV is comprised of transfer gate NTS1 and inverters IVS1, IVS2, and IVS3.
The specific connections are that the input terminal of transfer gate NTS1 is connected to the output terminal of inverter IVM3 in master latch MST, and the output terminal is connected to the input terminal of inverter IVS1 and output terminal of inverter IVS2.
Also, the output terminal of inverter IVS1 is connected to the input terminals of inverters IVS2 and IVS3, and the output terminal of inverter IVS2 is connected to the input terminal of inverter IVS1.
Namely, inverters IVS1 and IVS2 are connected between the input terminal of inverter IVS3 and the output terminal of transfer gate NTS1 in parallel with the input/output terminals in the opposite orientation.
Inverter IVS2 is comprised of a high-resistance inverter for safe operation of the circuit and prevention of through current.
Also, each gate terminal of each transfer gate NTM1, NTM1n, NTMs and NTS1 is connected respectively to the control system through the signal line, not shown in the figure, and prescribed level in which the timing is controlled by said control system, for example, clock signals of 5 V are input.
Specifically, clock signal MCLK1 is input into the gate terminal of transfer gate NTM1, and clock signal MCLKn is input into the gate terminal of transfer gate NTM1n. Said first clock signals (1,n) do not become high level at the same time.
Also, scan clock signal SCANCLK for device test is input into the gate terminal of transfer gate NTMs.
On the other hand, clock signal SCLK in which the phase differs from clock signal MCLK (1,n) is input into the gate terminal of transfer gate NTS1.
FIGS. 16a and 16b are timing charts showing the relationship between clock signal MCLK and clock signal SCLK.
As shown in FIGS. 16a and 16b, clock signal MCLK and clock signal SCLK are out of phase by 180.degree., and so-called isolation time IT is provided in which both signals become low level in order to prevent clock skew.
Therefore, input of the clock signals is controlled so that when transfer gate NTM1 or NTM1n of master latch MST is in the ON state, transfer gate NTS1 of slave latch SLV maintains the OFF state, and when transfer gate NTS1 of slave latch SLV is in the ON state, transfer gate NTM1 or NTMn of master latch MST maintains the OFF state.
Transfer gate NTMs for scanning is provided for testing of the device and scan clock SCANCLK input into the gate terminal of said transfer gate NTMs is input with the same timing as clock signal MCLK.
Namely, the input of the clock signals is controlled during the device test so that when transfer gate NTMs for scanning is in the ON state, transfer gate NTS1 of slave latch SLV maintains the OFF state, and when transfer gate NTS1 of slave latch SLV is in the ON state, transfer gate NTMs for scanning maintains the OFF state.
Here, the operation of a case when data in high level "1" of 5 V is input into input terminal DIN1 will be explained in the constitution of FIG. 15.
When data at high level "1" of 5 V is input into input terminal DIN1, transfer gate NTM1 takes on the ON state if clock signal MCLK1 is input into the gate terminal of transfer gate NTM1 at high level of 5 V.
By it, the input data of high level 5 V passes through transfer gate NTM1 but at this time, level at output terminal side node ND1 of transfer gate NTM1 becomes about 3.5 V due to the substrate effect and threshold value voltage V.sub.thN (about 1 V) of transfer gate NTM1, and this level is applied to the input terminal of inverter IVM1.
The circuit threshold value of inverter IVM1 is generally set at about 1/2 of power voltage V.sub.DD or a level slightly lower than that so the output side becomes a low level due to the level inversion function of inverter IVM1. At this time, the input level is 3.5 V which is lower than 5 V so some through current flows.
Low level which is the output of inverter IVM1 is applied to the input terminal of inverter IVM2 and inverter IVM3.
Inverter IVM2 is constituted with a high-resistance type inverter as it was noted above, the output which received low level becomes about 5 V, and high level if 5 V is applied to the input terminal of inverter IVM1.
Namely, the data level which decreased to about 3.5 V due to the substrate effect or threshold voltage V.sub.thN of transfer gate NTM1 is compensated and flow of through current is suppressed; thus, the high level is stably maintained.
Next, clock signal MCLK1 becomes low level and when clock signal SCLK is input into gate terminal of transfer gate NTS1 in slave latch SLV at high level, transfer gate NTM1 takes on the OFF state and transfer gate NTS1 takes on the ON state.
By it, high level output of inverter IVM3 in master latch MST passes through transfer gate NTS1 but at this time, as in the case of master latch MST, the level in output terminal side node ND2 of transfer gate NTS1 becomes about 3.5 V due to the substrate effect and threshold voltage V.sub.thN of transfer gate NTS1, and this level is applied to the input terminal of inverter IVS1.
The circuit threshold value of inverter IVS1 is set at about 1.2 of power voltage V.sub.DD or a level slightly lower than that, as noted above, so the output side becomes low level due to the level inversion function of inverter IVS1. At this time, the input level is 3.5 V which is lower than 5 V so some through current flows.
Low level which is output of inverter IVS1 is applied to the input terminal of inverter IVS3 and inverter IVS2.
Inverter IVS2 is constituted with a high-resistance type inverter, as noted above, the output which received low level becomes about 5 V, and this high level of 5 V is applied to the input terminal of inverter IVS1.
Namely, the data level which dropped to about 3.5 V due to the substrate effect and threshold value voltage V.sub.thN of transfer gate NTS1 is compensated, and the flow of through current is suppressed; thus, the level is stably maintained.
Thus, a stabilized high-level output is obtained from inverter IVS3 and output from data output terminal DOUT.
As noted above, the circuit in FIG. 15 is stably operated as a shift register which shifts the data successively with clock signal MCLK and clock signal SCLK under power voltage V.sub.DD of 5 V.
However, from the need to reduce power consumption in recent years and to secure reliability in fine ICs, the bottom limit for power voltage V.sub.DD of 3.0 V or 2.7 V and depending on the application, a need to secure operation at even lower voltage is being created.
When power voltage V.sub.DD is decreased, not only is a considerable decrease in the operational speed of the IC created, but, in shift register circuits, etc., there was the problem of sufficient propagation of a high level not being possible due to said substrate effect or threshold value voltage V.sub.thN of the transistor itself when propagating high level in n-channel transfer gates thus the operation became defective.
The level, after propagating through the transfer gate, becomes approximately (V.sub.DD -V.sub.thN) and under low power voltage, the propagated level becomes lower than the decrease in power voltage V.sub.DD.
The circuit threshold value with inverter receiving this level is set to about 1/2 of power voltage V.sub.DD or a level slightly lower than that under realistic beta ratio in the design so in order to transmit sufficient level over said circuit threshold value to the node after propagating through the transfer gate, it is necessary to decrease the threshold value voltage V.sub.thN or raise the gate voltage.
In order to solve this problem, it has been proposed to change the manufacturing process to a process of lowering the threshold value voltage V.sub.thN by decreasing, for example, the p-type concentration of n-type channels.
However, the gate length of the transistor in VLSI has reached the area of submicrons in recent years, and sufficient punchthrough pressure resistance cannot be secured when threshold value voltage V.sub.thN is decreased too much. Also, even when the transistor is in the OFF state, it is necessary to solve various problems during the mass production such as the so-called subthreshold current due to the short channel effect in which the current flows due to widening of the depletion layer from the drain, etc.
Also, improving the control of loss in the yield created by the above is also a load in the process and even if threshold value voltage V.sub.thX(-N, P) is decreased to a realistic value, the situation will become difficult requiring that consideration also be given to the margin with respect to the variance in the manufacture in order to secure power voltage V.sub.DD =2.7 V in said circuits.
Furthermore, when shrinkage of 65 .mu.m/0.5 .mu.m, etc., are also included in the consideration, the situation becomes even more difficult in the future.
Therefore, with respect to the operational need for power voltage V.sub.DD =less than 2.7 V, a so-called complete CMOS type shift register is generally known conventionally with a constitution which replaced all n-channel transfer gates NTM1, NTM1n, NTMs, and NTS1 in FIG. 15 with transfer gates CTM1, CTM1n, CTMs, and CTS1 composed of complementary type MOS (CMOS: complementary MOS) in which a decrease in power consumption and enhancement of the speed are possible like that which is shown in FIG. 17.
In this complete CMOS type shift register, along with inputting clock signals MCLK1, MCLKn, and SCANCLK to each gate terminal of N-MOS transistors N1, Nn, and Ns constituting each CMOS transfer gate CTM1, CTM1n, and CTMs of master latch MST, by inputting inverted clock signals XMCLK1, XMCLKn, and XSCANCLK which inverted clock signals MCLK1, MCLKn, and SCANCLK to each gate terminal of P-MOS transistors P1, Pn, and Ps which constitute each CMOS transfer gate CTM1, CTM1n, and CTMs, each transfer gate CTM1, CTM1n, and CTMs are turned ON/OFF.
Similarly, along with inputting clock signal SCLK to the gate terminal of N-MOS transistor NS constituting CMOS transfer gate CTS1 of slave latch SLV, by inputting inverted clock signal XSCLK which inverted clock signal SCLK into the gate terminal of P-MOS transistor PS constituting CMOS transfer gate CTS1, transfer gate CTS1 is turned ON/OFF.
Also, FIGS. 18a-18d show the timing relationship of clock signal MCLK and inverted clock signal XMCLK, the timing relationship of clock signal SCLK and inverted clock signal XSCLK, and the timing relationship between the mutual clock signals.
As shown in FIGS. 18a-18d, the phase of clock signal MCLK and clock signal SCLK or inverted clock signal XMCLK and inverted clock signal XSCLK is displaced by 180.degree., and moreover, a so-called isolation time IT in which both signals become low level is provided in order to prevent clock skew.
The complete CMOS type shift register with this type of constitution operates stably as a shift register which shifts the data successively with clock signal MCLK and clock signal SCLK even under power voltage V.sub.DD =2.7 V.
However, a complete CMOS type shift register needs to provide clock signals to N-MOS transistors N1, Nn, Ns, and NS and P-MOS transistors N1, Nn, Ns, and NS which constitute each CMOS transfer gate CTM1, CTM1n, CTMs, and CTS1, and when the input of data increases, a clock count of double the number becomes necessary.
As a result, securing a fixed spacing with respect to the respective transistor and separation with wells become necessary caused by the increase in the layout area due to the wiring and the polarity of the p-channel and n-channel transfer gates being different.
Also, increase in the timing circuit for preventing clock skew or caution with respect to the clock skew of the p-channel and n-channel with enhancement in the speed of the IC becomes unavoidable and causes an increase in area. Also, buffer for p-channel drive also becomes necessary so it leads to an increase in the layout area. In the data bus, etc., the circuit scale of the clock driver increases since arithmetic is executed by selecting from a number of data inputs and, in this type of circuit state, a considerable increase in the layout area is generated.